Identification of unknown sources for logic built-in self test in verification

ABSTRACT

A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. Responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, the tool determines whether a latch of the one or more latches is corrupted by an unknown source. The tool gathers each of the one or more latches determined to be an unknown source after a capture clock phase. The tool performs a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source. The tool verifies that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

BACKGROUND OF THE INVENTION

The present invention relates generally to circuit verification, andmore particularly to identifying unknown sources for logic built-in selftest in verification.

Logic built-in self test (LBIST) is a test method that executes a maintest loop of a chip (circuit) with minimal dependences on an externaltester. This approach of testing uses a pseudo random pattern generator(PRPG) to provide a pattern stimulus, and a multi input signatureregister (MISR) to capture a response. An on product clock generator(OPCG) logic generates a clock sequence for testing. The PRPG generatesa test pattern that is applied into the LBIST scan channels via a scan.The response from the scan channels after a capture clock sequence iscompressed in MISR(s), which is generally termed a signature. Once thechip is initialized, only a reference clock is needed from the testequipment or circuit board, therefore MISR(s) have an advantage ofefficiently compressing the response data. To have a well definedsignature in a MISR at the end of a test, all response data collectedinto the MISR must be predictable, and as such, there cannot be anyX-states in the chip going to a MISR. For example, where there is atiming sensitive path that gives a deterministic response only after twocycles, this would be considered an X (i.e., an unknown) for one cycletests, and must be blocked from being captured into a MISR.

SUMMARY

Aspects of an embodiment of the present invention disclose a method,system, and computer program product for determining unknown sources ina circuit design for exclusion from logic built-in self test (LBIST)verification for the circuit. Responsive to initializing each of one ormore latches in one or more test channels of the circuit design beingtested, the method includes determining, by one or more computerprocessors, whether a latch of the one or more latches is corrupted byan unknown source. The method includes gathering, by one or morecomputer processors, each of the one or more latches determined to be anunknown source after a capture clock phase. The method includesperforming, by one or more computer processors, a backward traverse oflogic circuitry feeding each of the one or more latches determined to bean unknown source. The method includes verifying, by one or morecomputer processors, that a fence on one or more unknown source netsassociated with each of the one or more latches blocked the unknownsource from contributing to a test signature.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a function block diagram illustrating a portion of a dataprocessing system, generally designated 100, in accordance with anembodiment of the present invention.

FIG. 2 is a flowchart depicting the steps of a simulation method fordetermining unknown sources in a circuit within a data processing system(such as data processing system 100) for exclusion from LBISTverification, generally designated 200, in accordance with an embodimentof the present invention.

FIG. 3 is an alternative view of FIG. 1, illustrating an exemplarymulti-cycle functional capture clock sequence in a circuit within a dataprocessing system (such as data processing system 100), generallydesignated 300, in accordance with an embodiment of the presentinvention.

FIG. 4 is an alternative view of FIG. 1, illustrating a functionalcapture clock sequence with latches configured at a n:1 ratio in acircuit within a data processing system (such as data processing system100), generally designated 400, in accordance with an embodiment of thepresent invention.

FIG. 5 is a flowchart depicting the steps of a method for insertingmissing fencing of X sources to achieve a stable test signature forLBIST in a circuit within a data processing system (such as dataprocessing system 100), generally designated 500, in accordance with anembodiment of the present invention.

FIG. 6 is a block diagram of components of a data processing system(such as data processing system 100), generally designated 600, depictedin accordance with the present invention.

DETAILED DESCRIPTION

Embodiments of the present invention recognize that state of the artmethods for verification relying on various text-based and formal designspecifications to identify an X (unknown) source are not fullyrepresentative of the unknown logic and are inaccurately translated totest cases and models resulting in test and coverage escape for part ofa circuit's logic. Embodiments of the present invention furtherrecognize that setting all latches in a design to X (unknown state) forsimulation does not cover special X-state cases, such as analogcomponents that are not deterministic, or arrays that are made of memorycells instead of latches, or control logic driving the test that can notbe set to X, but is nevertheless not contributing predictable values.

Embodiments of the present invention provide the capability to identifypre-silicon all unknown sources that could contribute to an unstablesignature and cover a plurality of special X-state cases. Embodiments ofthe present invention provide the capability to utilize nets/signals ina chip (electronic circuit) and special properties of various latches inthe chip's design to identify the unknown sources that could contributeto an unstable signature test methods compressing test results into asignature, including, but not limited to, LBIST.

Implementation of such embodiments may take a variety of forms, andexemplary implementation details are discussed subsequently withreference to the Figures.

As will be appreciated by one skilled in the art, aspects of the presentinvention may be embodied as a method or system. Accordingly, aspects ofthe present invention may take the form of an entirely hardwareembodiment, an entirely software embodiment (including firmware,resident software, micro-code, etc.), or an embodiment combiningsoftware and hardware aspects that may all generally be referred toherein as a “circuit,” “module,” or “system.” Furthermore, aspects ofthe present invention may take the form of a computer program productembodied in one or more computer-readable media having computer readableprogram code/instructions embodied thereon.

The present invention will now be described in detail with reference tothe Figures. FIG. 1 illustrates an exemplary data processing system 100incorporating certain components for identifying unknown sources forlogic built-in self-test verification. In the exemplary embodiment, dataprocessing system 100 may be implemented in a plurality of processorarchitectures that issue and execute instructions, such as single ormulti-core microprocessors or micro controllers. Data processing system100 includes a device under test (DUT) 102.

Generally, DUT 102 represents a chip (circuit) to be verified. Manymodern circuits include a plurality of scan paths, and as such, DUT 102includes a plurality of scan paths, such as scan path(s) 122 a and 122b. Data processing system 100 applies an LBIST test pattern to DUT 102,which generates a plurality of LBIST patterns, applying the plurality ofLBIST patterns to scan path(s) 122 a and 122 b. Multi input signatureregister (MISR) 124 compresses each output from logic 104 resulting fromthe LBIST patterns into a signature, such as signature 126, forverification.

In the exemplary embodiment, data processing system 100 includes a logicbuilt-in self-test (LBIST) engine 108. In the exemplary embodiment,LBIST 108 is an otherwise conventional LBIST engine. LBIST engine 108generates an LBIST test pattern based, at least in part, on user input.In one embodiment, LBIST engine 108 includes a plurality of LBISTcomponents, such as a controller, for determining unpredictable elementsin an electronic circuit under test, such as DUT 102, for exclusion fromLBIST verification.

In the exemplary embodiment, DUT 102 includes a pseudo random patterngenerator (PRPG) 106. PRPG 106 is an otherwise conventional pseudorandom pattern generator, configured to generate a plurality of orderedpseudo random LBIST test patterns in response to an LBIST test patternreceived from LBIST engine 108. Generally, the LBIST test patternsgenerated by PRPG 106 are configured, collectively, to test for a widevariety of problems and faults in logic 104. For convenience, as usedherein, “LBIST test patterns” means the pseudo random patterns generatedby PRPG 106 in response to an LBIST test pattern.

In the exemplary embodiment, DUT 102 includes MISR 124 for compressingoutput into a data signature. MISR 124 is an otherwise conventionalmulti input signature register or any other suitable data compactor. Inone embodiment, MISR 124 can be fully integrated, partially integrated,or separate from DUT 102. MISR 124 receives raw output from logic 104(resulting from LBIST pattern stimuli), and compresses the raw outputinto a signature, such as signature 126. There are a variety of wellknown approaches to compacting raw output into a signature.

In the exemplary embodiment, DUT 102 includes a signature 126.Generally, signature 126 is an otherwise conventional signature file,and can comprise a storage structure, hardware storage, an abstract datastructure, or other suitable configuration. In one embodiment, signature126 stores a known good signature output for each test pattern appliedto logic 104. In an alternate embodiment, signature 126 stores aplurality of known good signature outputs for a plurality of LBISTpatterns.

In the exemplary embodiment, LBIST engine 108 applies an LBIST patternto logic 104, from which PRPG 106 generates LBIST patterns for one ormore scan paths, such as scan path(s) 122 a and 122 b. Logic 104provides an output to MISR 124, which compresses the raw output datainto signature 126.

In the exemplary embodiment, a latch or memory element, such as latch110 and 112 that is connected along one or more scan paths to MISR 124,such as scan path(s) 122 a and 122 b respectively, contribute tosignature 126. In order for a signature, such as signature 126, to bestable, each latch, such as latch 110 and 112 must be known andpredictable. One or more nets, such as net 118, 120 a, and 120 b arefunctional paths contributing to logic 104. In the exemplary embodiment,net 118 is initialized by PRPG 106 in a same clock domain as latch 112(i.e., it is driven by latch 110 fed by PRPG 106 along scan path 122 a),and as such, is considered a known source. In the exemplary embodiment,net 120 a and 120 b are not initialized by PRPG 106 in the same clockdomain as latch 112, and as such, are treated as an X source (i.e.,unknown source) for LBIST. LBIST engine 108 determines all possiblenets, such as net 120 a and 120 b, originating from an unknown source,such as X source 114 and X source 116, respectively, that arecontributing to logic, such as logic 104, of elements under test, suchas latch 112, that are collected into MISR 124.

In the exemplary embodiment, X source 114 and X source 116 are unknownsources that, when contributing to a MISR signature during LBISTverification, render the signature unstable. X source 114 and X source116 can include, without limitation, typical unknown sources such asarrays, analog components, clock domain crossings, phase locked loopcomplexes (PLLs), and on-product clock generator blocks (OPCGs).

In one embodiment, a latch, such as latch 112 can be included in morethan one group of latches. For example, latch 112 contributing tosignature 126 is generally also initialized during verification by PRPG106 similar to latch 110. In one embodiment latch 110 and latch 112 caninclude groups of latches. For example, latch 110 can represent a groupof latches initialized by PRPG 106.

Data processing system (DPS) 100 may include additional components, suchas LBIST engines, MISRs, PRPGs, controllers, scan paths, latches, Xsources, combinatorial logic, etc., not depicted in FIG. 1.

FIG. 2 is a flowchart depicting logical operational steps of asimulation method performed by, for example, DPS 100, for determiningunknown sources in a circuit for exclusion from LBIST verification,generally designated 200, in accordance with an embodiment of thepresent invention.

DPS 100 determines an initial nets list (202). In the exemplaryembodiment, DPS 100 determines an initial nets list by collecting eachof one or more nets within a circuit design being tested (i.e.,verified), and compiling the collected nets in the initial nets list.For example, DPS 100 collects each of the one or more nets, such as net118, net 120 a, and net 120 b, within the circuit design of a circuitunder test, such as DUT 102, and compiles the one or more nets in theinitial nets list. The initial nets list contains both known sources andX sources, and can be a gate-level net list, or an intermediate net listproduced for simulation, representative of the circuit design beingtested.

DPS 100 initializes the one or more nets contained in the initial netslist, where initializing each of the one or more nets includesconfiguring each of the one or more nets as an unknown source (204). Forexample DPS 100 initializes net 118, net 120(a), and net 120(b) byconfiguring each of the nets as an X (unknown) source.

DPS 100 configures a phase locked loop (PLL) block for a desired systemclock frequency (206), and hence removes the initialization to X fromthe associated nets in DUT 102, such as net 118, net 120(a), and net120(b). For example, where X source 114 was part of the PLL, net 120(a)is now driven by X source 114 and the X (unknown) value is removed fromthat net.

DPS 100 configures test logic to operate within a desired test mode(208). In the exemplary embodiment, DPS 100 configures the test logic tooperate with LBIST testing. For example, nets driven by PRPG 106, suchas net 118, are no longer configured at an X (unknown) value.

DPS 100 configures one or more fences designed to block unknown sources(210). In the exemplary embodiment, DPS 100 configures one or morefences, such as control latches, gates, etc., to block unknown sources,such that outputs of the fences are free of X (i.e., free of unknownsources and well defined).

DPS 100 determines a second nets list (212). In the exemplaryembodiment, DPS 100 determines the second nets list by collecting eachof one or more nets that are now free of unknown sources after step 208and 210 (i.e., the fenced nets and the outputs of the fenced nets), andremoving each of the one or more nets that are free of unknown sourcesfrom the initial nets list, thereby avoiding consideration of nets thatare known to be defined for X (unknown) source detection.

DPS 100 programs clock control logic to a desired clock control sequence(214). In the exemplary embodiment, DPS 100 programs the clock controllogic to a desired clock control sequence for LBIST testing, wherein thedesired clock control sequence is determined by a circuit's (i.e.,device under test) design and conventional simulation procedures.

DPS 100 initializes each of one or more latches in one or more testchannels (216). In the exemplary embodiment, DPS 100 initializes each ofthe one or more latches, such as latch 110 and latch 112, in the one ormore test channels, such as scan path(s) 122 a and 122 b, respectively,by PRPG scan loading or parallel loading of latches using conventionalverification environment capabilities.

DPS 100 removes each of the one or more nets initialized in response tothe initialization of each of the one or more latches in the one or moretest channels (218). In the exemplary embodiment, DPS 100 removes eachof the one or more nets initialized such that the initial nets listcontains all the probable unknown sources for the logic under test. Forexample, DPS 100 removes net 118 from the X net list.

DPS 100 initializes LBIST testing (220). In the exemplary embodiment,DPS 100 initializes, for example, an on product clock generator engine(OPCG) for LBIST testing to analyze the circuit design and determinewhether the MISR signature, such as signature 126, is corrupted with Xsources.

DPS 100 initializes all of the nets in the initial nets list, settingthe nets to X (i.e., unknown) sources just prior to a capture phase ofthe LBIST testing (222).

DPS 100 determines whether any latch in the LBIST scan path(s), such asscan path(s) 122 a and 122 b, feeding a MISR, such as MISR 124, iscorrupted with an X source (224). In the exemplary embodiment, DPS 100determines whether any latch in the LBIST scan path(s) is corrupted withan X source by determining if a latch, such as latch 110 and 112, or Xsource 114 and 116, contributing to a MISR signature, such as signature126, is an unknown source. For example, in the case where a latch, suchas X source 116, is contributing a MISR signature, DPS 100 may determinethat X source 116 is in fact an unknown source corrupting the MISRsignature. In another example, in the case where a latch, such as latch110, is contributing to a MISR signature, DPS 100 may determine thatlatch 110 is in fact a known source, as it originates from a PRPG, suchas PRPG 106, and therefore is not corrupting the MISR signature.

In the case where DPS 100 determines that a latch contributing to a MISRsignature is an unknown source (YES branch, 224), DPS 100 initiates adesign fix mechanism to block the unknown source(s) (226). The designfix mechanism is subsequently discussed in further detail in referenceto FIG. 5.

In the exemplary embodiment, where DPS 100 determines that no latchcontributing to the MISR signature is an unknown sources (NO branch,224) (i.e., verification of the design is achieved using a simulationmodel), DPS 100 iterates steps 214-224 multiple times using differentclock sequences and test patterns to have enough randomness for logic100 to propagate X sources to the input of one or more latches (228).

FIG. 3 is an alternative view of FIG. 1, illustrating an exemplarymulti-cycle functional capture clock sequence in a circuit within a dataprocessing system (such as data processing system 100), generallydesignated 300, in accordance with an embodiment of the presentinvention.

In the exemplary embodiment, a test sequence may contain more than onefunctional capture clocks to test multi-cycle paths. In the case of atest sequence with two or more functional capture clocks, a trace backof two or more levels of latches and/or memory elements in the logicpath is necessary to determine all X sources in the given test pattern.

In the exemplary embodiment, a two functional capture clock sequence isdepicted, including latch 302, latch 304, latch 306, x source 308, andlatch 310. Latches 302, 304, and 306 are each known sources since eachlatch is driven from a PRPG, such as PRPG 106, for one functionalcapture clock sequence. If two functional capture clocks are applied,then it becomes necessary to traverse back one level of logic to, forexample, logic 312 and logic 314, contributing to latches 302 and 304respectively. Latch 302 is driven by another known value, i.e., latch306, and therefore remains a known source for a two functional clockssequence. In contrast, latch 304 is driven by at least the x source 308,and as such, latch 304 becomes an X (unknown) source itself for the twofunctional clocks sequence. In the exemplary embodiment, backwardtraversing can occur for one or more levels of logic, such as level 1and level 2 depicted in FIG. 3, depending on a number of cycle paths anda level or accuracy in verification of a design.

FIG. 4 is an alternative view of FIG. 1, illustrating a functionalcapture clock sequence with latches configured at a n:1 ratio in acircuit within a data processing system (such as data processing system100), generally designated 400, in accordance with an embodiment of thepresent invention.

In the exemplary embodiment, the simulation method discuss above in FIG.2 and FIG. 3 can be extended to latches operating at a n:1 ratio (i.e.,latches that are clocked once every n cycles). Such latches are stablefor n functional capture clocks, as they are not clocked more often. Forexample, as depicted in FIG. 4, in a group of latches, including latch402, latch 406, and latch 408 operating at 1:1 ratio (full frequency),latch 404 operating at 2:1 ratio, and an X source 410, latch 404 isstable for one backward traversal level (e.g., level 1 of FIG. 4) beforeit is clocked and captures the X source 410 value, and latch 402 isstable for two functional capture clocks (e.g., level 2 of FIG. 4), aseach latch is a known source driven from PRPG 106. In the exemplaryembodiment, latch 112 will only be corrupted where at least threefunctional capture clocks (e.g., level 3 of FIG. 4) are applied duringLBIST testing.

In another embodiment, a full structural analysis of a design at gatelevel can be used to determine whether all latches contributing to aMISR signature are known sources (i.e., stable). Similarly, a net listof all latches that are set to a known value by a PRPG can be identifiedby a full structural analysis of the design. Finally, a full structuralanalysis of a logic back cone (i.e., logic) of all latches of a knownsource can be done to determine whether any other sources, such asunknown sources, can be reached in a n level, where n is a number offunctional capture clocks of a test sequence. For example, if adiscovered source is not a known source, for example, the discoveredsource is an X source, then the signature will not be stable and thedesign must be modified to fix this problem.

In yet another embodiment, a half structural analysis of a design atgate level, using steps 202-212 of the simulation method described inFIG. 2, is performed to generate a net list. In response to generatingthe net list, DPS 100 performs a structural analysis of the net list ata gate level to traverse backward from each of the latches in a group oflatches to determine whether a latch hits a net/latch contained in thenet list. In the case where a latch hits a net/latch contained in thenet list, it can be inferred that a MISR signature will not be stable.

FIG. 5 is a flowchart depicting the steps of a method for insertingmissing fencing of X sources to achieve a stable test signature forLBIST in a circuit within a data processing system (such as dataprocessing system 100), generally designated 500, in accordance with anembodiment of the present invention.

DPS 100 gathers as input each of the latches determined to be unknown instep 224 of FIG. 2 (502). In the exemplary embodiment, DPS 100 gathersas input each of the latches by generating a list of test participatinglatches that are determined to be an X source (i.e., unknown) after acapture clock phase.

DPS 100 performs a backward traverse of logic feeding each of thelatches that are determined to be an X source (504). In the exemplaryembodiment, DPS 100 performs a trace back of the logic feeding eachlatch in the design determined to be an X source as previously describedin FIGS. 3 and 4.

DPS 100 determines one or more X source nets and one or more fence(i.e., gate) locations (506). In the exemplary embodiment, DPS 100determines one or more X source nets for each of the latches that aredetermined to be an X source, wherein the one or more X source nets arefunctional paths from the X source to the logic. In the exemplaryembodiment, DPS 100 determines the one or more fence locations for eachof the latches that are determined to be an X source, wherein the one ormore fence locations are on the one or more X source nets.

DPS 100 blocks one or more X sources with a fence (508). In theexemplary embodiment, DPS 100 blocks the one or more X sources with afence by placing a fence on the one or more X source nets associatedwith the one or more X sources.

DPS 100 repeat steps 202-212, as described in FIG. 2, to verify the fix(510). In the exemplary embodiment, DPS 100 performs steps 202-212 againto determine that a fence on one or more X source nets associated withan X source actually blocks the X source from contributing to a MISRsignature. If DPS 100 verifies that the fence eliminates the X sourcefrom the MISR signature (YES branch, 510), then the fix is successful.If DPS 100 cannot verify that the fence blocked the X source from theMISR signature (NO branch, 510) (i.e., the X source still contributes tothe MISR signature), then DPS 100 repeats steps 502-510 to eliminate theX source from the MISR signature.

FIG. 6 is a block diagram of components of a data processing system(such as data processing system 100), generally designated 600, depictedin accordance with the present invention.

FIG. 6 depicts a block diagram of components of a data processingsystem, such as data processing system 100, in accordance with anillustrative embodiment of the present invention. It should beappreciated that FIG. 6 provides only an illustration of oneimplementation and does not imply any limitations with regard to theenvironments in that different embodiments may be implemented. Manymodifications to the depicted environment may be made.

In the illustrative embodiment, data processing system 100 is shown inthe form of a general-purpose computing device, such as computer system610. The components of computer system 610 may include, but are notlimited to, at least one processor or processing unit 614, a systemmemory 624, and a bus 616 that couples various system componentsincluding system memory 624 to processing unit 614.

Bus 616 represents one or more of any of several types of busstructures, including a memory bus or memory controller, a peripheralbus, an accelerated graphics port, and a processor or local bus usingany of a variety of bus architectures. By way of example, and notlimitation, such architectures include Industry Standard Architecture(ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA)bus, Video Electronics Standards Association (VESA) local bus, andPeripheral Component Interconnect (PCI) bus.

Computer system 610 typically includes a variety of computer systemreadable media. Such media may be any available media that is accessibleby computer system 610, and it includes both volatile and non-volatilemedia, removable and non-removable media.

System memory 624 can include computer system readable media in the formof volatile memory, such as random access memory (RAM) 626 and/or cachememory 628. Computer system 610 may further include otherremovable/non-removable, volatile/non-volatile computer system storagemedia. By way of example only, storage system 630 can be provided forreading from and writing to a non-removable, non-volatile magnetic media(not shown and typically called a “hard drive”). Although not shown, amagnetic disk drive for reading from and writing to a removable,non-volatile magnetic disk (e.g., a “floppy disk”), and an optical diskdrive for reading from or writing to a removable, non-volatile opticaldisk such as a CD-ROM, DVD-ROM, or other optical media can be provided.In such instances, each can be connected to bus 616 by one or more datamedia interfaces. As will be further depicted and described below,system memory 624 may include at least one computer program producthaving a set (e.g., at least one) of program modules that are configuredto carry out the functions of embodiments of the invention.

Program/utility 632, having one or more sets of program modules 634, maybe stored in memory 624 by way of example, and not limitation, as wellas an operating system, one or more application programs, other programmodules, and program data. Each of the operating systems, one or moreapplication programs, other program modules, and program data, or somecombination thereof, may include an implementation of a networkingenvironment. Program modules 634 generally carry out the functionsand/or methodologies of embodiments of the invention as describedherein. Computer system 610 may also communicate with one or moreexternal device(s) 612 such as a keyboard, a pointing device, a display622, etc., or one or more devices that enable a user to interact withcomputer system 610 and any devices (e.g., network card, modem, etc.)that enable computer system 610 to communicate with one or more othercomputing devices. Such communication can occur via Input/Output (I/O)interface(s) 620. Still yet, computer system 610 can communicate withone or more networks such as a local area network (LAN), a general widearea network (WAN), and/or a public network (e.g., the Internet) vianetwork adapter 618. As depicted, network adapter 618 communicates withthe other components of computer system 610 via bus 616. It should beunderstood that although not shown, other hardware and softwarecomponents, such as microcode, device drivers, redundant processingunits, external disk drive arrays, RAID systems, tape drives, and dataarchival storage systems may be used in conjunction with computer system610.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be any tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium can be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network can comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention can be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions can execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer can be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection can be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) can execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions can be provided to aprocessor of a general purpose computer, a special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionscan also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions can also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams can represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block can occur out of theorder noted in the Figures. For example, two blocks shown in successioncan, in fact, be executed substantially concurrently, or the blocks cansometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the invention.The terminology used herein was chosen to best explain the principles ofthe embodiment, the practical application or technical improvement overtechnologies found in the marketplace, or to enable others of ordinaryskill in the art to understand the embodiments disclosed herein.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Itshould be appreciated that any particular nomenclature herein is usedmerely for convenience and thus, the invention should not be limited touse solely in any specific function identified and/or implied by suchnomenclature. Furthermore, as used herein, the singular forms of “a”,“an”, and “the” are intended to include the plural forms as well, unlessthe context clearly indicates otherwise.

What is claimed is:
 1. A method for determining unknown sources in acircuit design for exclusion from logic built-in self test (LBIST)verification for the circuit, the method comprising: responsive toinitializing one or more latches in one or more test channels of thecircuit design being tested, determining, by one or more computerprocessors, whether at least one latch of the one or more latches iscorrupted by an unknown source; responsive to a determination that atleast one of the one or more latches is corrupted by the unknown source,gathering, by the one or more computer processors, the at least onecorrupted latch after a capture clock phase; performing, by the one ormore computer processors, a backward traverse of logic circuitry feedingthe at least one corrupted latch; determining, by the one or morecomputer processors, one or more unknown source nets and one or morefence locations associated with the at least one corrupted latch;blocking, by the one or more computer processors, the unknown sourcewith a fence on the one or more unknown source nets associated with theunknown source; and verifying, by the one or more computer processors,that the fence on the one or more unknown source nets associated withthe at least one corrupted latch blocked the unknown source fromcontributing to a test signature.
 2. The method of claim 1 furthercomprises: determining, by the one or more computer processors, aninitial nets list, wherein determining the initial nets list includescollecting each of one or more nets within the circuit design beingtested, wherein the one or more nets include both known sources andunknown sources.
 3. The method of claim 1 further comprises:initializing, by the one or more computer processors, one or more netscontained in an initial nets list; and configuring, by the one or morecomputer processors, each of the one or more nets as an unknown source.4. The method of claim 1 further comprises: determining, by the one ormore computer processors, a second nets list, wherein determining thesecond nets list includes collecting each of one or more nets that arefree of unknown sources; and removing, by the one or more computerprocessors, each of the one or more nets that are free of unknownsources from the initial nets list to avoid consideration of those knownsources during unknown source detection.
 5. The method of claim 4further comprises: configuring, by the one or more computer processors,test logic circuitry to operate within a desired test mode; configuring,by the one or more computer processors, one or more fences designed toblock unknown sources, such that an output of the one or more fences isfree of unknown sources; and collecting, by the one or more computerprocessors, each of the one or more nets that is the output of the oneor more fences.
 6. The method of claim 1 further comprises: removing, bythe one or more computer processors, one or more nets initialized inresponse to initialization of each of one or more latches in one or moretest channels; and initializing, by the one or more computer processors,each of the one or more latches in the one or more test channels.
 7. Themethod of claim 1 further comprises: initializing, by the one or morecomputer processors, all of one or more nets in an initial nets list,and setting the one or more nets to unknown sources prior to a capturephase of LBIST testing.
 8. The method of claim 1 further comprises:responsive to determining that a latch of the one or more latches iscorrupted by the unknown source, initiating, by the one or more computerprocessors, a circuit design element to block the unknown source.
 9. Acomputer system for determining unknown sources in a circuit design forexclusion from logic built-in self test (LBIST) verification for thecircuit, the computer system comprising: one or more computerprocessors; one or more computer readable storage media; programinstructions stored on at least one of the one or more computer readablestorage media for execution by at least one of the one or more computerprocessors, the program instructions comprising: responsive toinitializing one or more latches in one or more test channels of thecircuit design being tested, program instructions to determine whetherat least one latch of the one or more latches is corrupted by an unknownsource; responsive to a determination that at least one of the one ormore latches is corrupted by the unknown source, program instructions togather the at least one corrupted latch after a capture clock phase;program instructions to perform a backward traverse of logic circuitryfeeding the at least one corrupted latch; program instructions todetermine one or more unknown source nets and one or more fencelocations associated with the at least one corrupted latch; programinstructions to block the unknown source with a fence on the one or moreunknown source nets associated with the unknown source; and programinstructions to verify that the fence on the one or more unknown sourcenets associated with the at least one corrupted latch blocked theunknown source from contributing to a test signature.
 10. The computersystem of claim 9 further comprises: program instructions todetermining, by one or more computer processors, an initial nets list,wherein determining the initial nets list includes collecting each ofone or more nets within the circuit design being tested, wherein the oneor more nets include both known sources and unknown sources.
 11. Thecomputer system of claim 9 further comprises: program instructions toinitialize one or more nets contained in an initial nets list; andprogram instructions to configure each of the one or more nets as anunknown source.
 12. The computer system of claim 9 further comprises:program instructions to determine a second nets list, whereindetermining the second nets list includes collecting each of one or morenets that are free of unknown sources; and program instructions toremove each of the one or more nets that are free of unknown sourcesfrom the initial nets list to avoid consideration of those known sourcesduring unknown source detection.
 13. The computer system of claim 12further comprises: program instructions to configure test logiccircuitry to operate within a desired test mode; program instructions toconfigure one or more fences designed to block unknown sources, suchthat an output of the one or more fences is free of unknown sources; andprogram instructions to collect each of the one or more nets that is theoutput of the one or more fences.
 14. The computer system of claim 9further comprises: program instructions to remove one or more netsinitialized in response to initialization of each of one or more latchesin one or more test channels; and initializing, by one or more computerprocessors, each of the one or more latches in the one or more testchannels.
 15. The computer system of claim 9 further comprises: programinstructions to initialize all of one or more nets in an initial netslist, and setting the one or more nets to unknown sources prior to acapture phase of LBIST testing.
 16. The computer system of claim 9further comprises: responsive to determining that a latch of the one ormore latches is corrupted by the unknown source, program instructions toinitiate a circuit design element to block the unknown source.
 17. Acomputer program product for determining unknown sources in a circuitdesign for exclusion from logic built-in self test (LBIST) verificationfor the circuit, the computer program product comprising: one or morecomputer readable storage media and program instructions stored on theone or more computer readable storage media, the program instructionscomprising: responsive to initializing one or more latches in one ormore test channels of the circuit design being tested, programinstructions to determine whether at least one latch of the one or morelatches is corrupted by an unknown source; responsive to a determinationthat at least one of the one or more latches is corrupted by the unknownsource, program instructions to gather the at least one corrupted latchafter a capture clock phase; program instructions to perform a backwardtraverse of logic circuitry feeding the at least one corrupted latch;program instructions to determine one or more unknown source nets andone or more fence locations associated with the at least one corruptedlatch; program instructions to block the unknown source with a fence onthe one or more unknown source nets associated with the unknown source;and program instructions to verify that the fence on the one or moreunknown source nets associated with the at least one corrupted latchblocked the unknown source from contributing to a test signature. 18.The computer program product of claim 17 further comprises: responsiveto determining that a latch of the one or more latches is corrupted byan unknown source, program instructions to initiate a circuit designelement to block the unknown source.